1. Field of the Invention
The present invention relates to an integrated semi conductor device containing an array of memory cells with markedly reduced chip's area requirements and wherein the need to form individually contacts on the drain area of all the cells is eliminated. The invention relates also to a process for fabricating such a memory device.
2. Description of the Prior Art
Monolithically integrated devices and memories using cells formed substantially by a MOS transistor (often a floating gate transistor) are well known and largely used in modern digital technologies. These semiconductor devices are characterized by the presence of one or more matrices of memory cells, either in the form of simple transistors and/or of floating gate type EPROM cells, organized in an array of rows and columns and which may be individually addressed by means of an appropriate selection circuitry.
Frequently in the case of EPROM memories, each cell may be essentially formed by a floating gate (or double gate) MOS transistor. The conventional architecture of these arrays of memory cells which is characterized by the presence of parallel interconnection lines for the individual drain contacts of the transistors (cells) of each column and which are oriented orthogonally with respect to the parallel gate lines is similarly well known. The source regions of a pair of adjacent transistors along a column are electrically in common and, according to a conventional arrangement, the pairs of source regions in common of the transistors (cells) disposed along the same row are electrically connected in common through the semiconducting silicon substrate. In these known devices the isolation structures which separates the drains and the gates of pairs of cells disposed on the same row have a substantially rectangular geometry, whether being formed in trenches cut into the semiconductor (e.g. BOX type isolations) or formed by thermally growing a thick layer of field oxide in purposely defined by means of a nitride mask isolation zones. Commonly the drain contacts are formed through a masking step followed by the etching of a dielectric layer deposited on the surface of the semiconductor wafer for isolating the gate lines (i.e. the control gate structures of the transistors) which have already been formed
From the point of view of photolithographic definition of increasingly small features, the above mentioned topographical arrangements of the conventional architecture of these devices have the following drawbacks.
Isolation Mask (or Active Areas Mask). The geometries, though perfectly rectangular on the master mask, inevitably show rounded corners when reproduced on wafer. This depends essentially from optical diffractive limits of the imagine systems. The latent image in the resist layer of the projected geometries already shows a rounding of corners, a rounding which further increases through the following developing process.
With high resolution optical apparatuses (e.g. with a N.A.&gt;0.45) and with a high contrast masking process, the phenomenon may be limited but persists. At present, the best result which may be obtained are corners with a radius of curvature of about a quarter of micrometer. This value increases when thermally growing a field oxide.
The rounding of corners of rectangular geometries determines an increased criticality of the alignment of the gate lines above and a certain dimensional variance of the channel width of the devices.
Contact Mask. The photolithographic problems are the known ones relating to the alignment in respect to the existing layers and to the rounding (which is here even more marked) of the corners of the geometries with a consequent reduction of the real contact area. Moreover the attendant reduction of the cross sectional area of the etched contact holes implies remarkable technological difficulties for adequately "filling" these submicrometric cavities with a metal.
In the prior U.S. patent application No. 07/632,101, filed on Dec. 20, 1990, of the same assignee, a memory device was described wherein the above mentioned technical problems were substantially overcome while permitting the achievement of a higher degree of compactness of the memory cell. This was obtained by forming continuous isolation strips instead of discontinuous strips implying a rectangular geometry and by attaining the connection in common of the source regions by means of metal interconnect lines formed in a self-alignment manner directly over the semiconductor substrate in the source areas and above the isolation strips at crossings with the latter. The general configuration was that of a device with source connection lines extending parallel to, and between, gate lines, while individual drain contacts were formed in a selfalignment manner on the respective drain areas between two adjacent isolation strips. The drain interconnection lines could then be formed in a conventional manner for connecting the drain areas belonging to unit cells of the same column. In other words, also according to this solution, the drain connection lines for connecting the individual drain contacts formed on the respective drain areas of the single cells run over the gate lines and were formed during relatively last phases of the fabrication process.
In the quest for devices ever more compact wherein submicrometric features must be defined by photolithographic methods, there is the need for further reducing the criticality of masking steps in terms of freedom from severe mask alignment tolerances, or more generally for simplifying the fabrication process with an ultimate objective of ensuring a high reliability and yield also in the case of devices designed for the most advanced limits of integration.